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Showing posts with label Flip flop. Show all posts
Showing posts with label Flip flop. Show all posts

## Triggering of Flip Flop|Master Slave Flip Flop

As we know that the flip flop is a bi-stable device or bi-stable synchronous device.In which Synchronous means(in respect to Triggering) at the time of triggering their was some slight changes in an output.

Triggering are of two types:-

1)Level Triggering
2)Edge Triggering

1)Level Triggering:-When the clock pulse goes high then Flip Flip can called  as Level Triggered Flip Flip.The main dis advantage of this flip flop is that it change stages many times when clock pulse is positive or negative for long time.

2)Edge Triggering Flip Flip:-When the positive transition is defined as positive and negative as negative then flip flop can called as Edge Triggered Flip Flop.

Now I discuss the Master Slave Flip Flop:-

Master Slave Flip Flip:-

Master Flip flip is used to handled the timing problem.S-R and J-K flip flop can't handled the timing problem.

Master Slave J-K Flip Flop:-

Master Slave Flip Flip is also drawn/constructed with JK Flip Flop.

In which the Red gates portion are called as Master flip fl0p and pink portion are called as slave flip flop.So the combination of Red and pink portion are called as Master Slave JK Flip Flop.

## All about T Flip Flop

T Flip Flop:-T flip flop stands for Toggle flip flop.It change the output when high signal is applied.

Truth Table:-

TQ(n+1)Q(n+1)'Action
0Q(n)Q(n)'No Change
1Q(n)'Q(n)Toggle

PS-NS Table(or Present State-Next State):-

Q(n)TQ(n+1)Q(n+1)'Action
0001No Change
0110Toggle
1010No Change
1001Toggle

Excitation Table or Application Table:-

Q(n)Q(n+1)T
000
011
101
110

Circuit Diagram of T flip flop using NAND gate:-

Circuit Diagram of T flip flop using NOR gate:-

JK flip flop is an electronic circuit in which a letter 'J' refer to set and 'k' refer to Reset.

Truth Table:-

JKQ(n+1)Q(n+1)'Action
00Q(n)Q(n)'No Change
0101Reset
1010Set
10Q(n)Q(n)Toggle

PS-NS Table(or Present State-Next State):-

Q(n)JKQ(n+1)Q(n+1)'Action
00001No Change
00101Reset
01010Set
011Q(n)'Q(n)Toggle
10010No change
10101Reset
11010Set
111Q(n)'Q(n)Toggle

Excitation Table or Application Table:-

Q(n)Q(n+1)JK
000X
011X
10X1
11X0

Circuit Diagram of J-K flip flop using NAND gate:-

Circuit Diagram of J-K flip flop using NOR gate:-

## All about D Flip Flop

D Flip Flop:-'D' stands for Delay so it is also called as delay flip flop.It delay the input by a clock pulse.It can either be construct with clock or non clock.

Truth Table:-

DQ(n+1)Q(n+1)'Action
001Reset
110Set

PS-NS Table(or Present State-Next State):-

Q(n)DQ(n+1)Q(n+1)'Action
0001Reset
0110Set
1001Reset
1010Set

Excitation Table or Application Table:-

Q(n)Q(n+1)D
000
011
100
111

Characteristic Equation of D flip flop:-

Q(n+1)=Q(n)'D+Q(n)D

=D(Q(n)'+Q(n))
=D

Circuit Diagram of D flip flop using NAND gate:-

Circuit Diagram of D flip flop using NOR gate:-

## What is Flip-Flops|Explain S-R Flip-Flop

Flip-Flop is a circuit which contains 2 outputs,one for normal value and other for opposite value or in simple words,it contains two states i.e. 0 and 1.

Type of Flip-Flop:-

1)S-R Flip-Flop

S-R Flip Flop:-

S-R stands for Set-Reset,in which reset means "clear".We can construct S-R flip flop with or without clock.In which '1'=Set and '0'=Reset.

Block Diagram of S-R flop flop:-

Truth Table:-

S R Q(n+1) Q(n+1)' Action
0 0 Q(n) Q(n)' No Change
0 1 01 Reset
1 0 10 Set
1 0 X X Forbidden

PS-NS Table(or Present State-Next State):-

Q(n) S R Q(n+1) Q(n+1)' Action
0 0 0l 0 1 No Change
0 0 1 0 1 Reset
0 1 0 1 0 Set
0 1 1 X X Forbidden
1 0 0 1 0 No change
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 X X Forbidden

Excitation Table or Application Table:-

Q(n) Q(n+1) S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0

Characteristic Equation of S-R flip flop:-

Q(n+1)=Q(n)'SR'+Q(n)R'

=R'(Q(n)S+Q(n))
=R'(Q(n)+s)
=Q(n)R'+SR'

Circuit Diagram of S-R flip flop using NAND gate:-

Circuit Diagram of S-R flip flop using NOR gate:-